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The Motorola 88000: A Lost RISC Innovation Ahead of Its Time

Introduction: The Motorola 88000 (m88k) and the RISC Revolution

The Motorola 88000, often shortened to m88k, represents a fascinating chapter in the history of computer architecture and a prime example of a "lost innovation." Developed by Motorola in the 1980s, the m88k was a RISC (Reduced Instruction Set Computer) instruction set architecture (ISA) intended to compete in the burgeoning workstation and high-performance computing markets.

Reduced Instruction Set Computer (RISC): A CPU design philosophy that favors a smaller set of simpler, faster instructions rather than a large set of complex instructions. RISC architectures aim to improve performance by executing instructions more quickly and efficiently.

Launched with the MC88100 processor in 1988, the m88k arrived on the scene after its rivals, SPARC (Sun Microsystems) and MIPS (MIPS Technologies). Despite its technical merits and forward-thinking design, the Motorola 88000 ultimately failed to achieve widespread commercial success. Its late entry to the market, compounded by delays in releasing its second-generation processor, the MC88110, limited its adoption primarily to Motorola's own MVME systems and niche embedded applications.

In 1991, Motorola's decision to join the AIM alliance – a collaboration with Apple and IBM to develop the PowerPC architecture – effectively signaled the end of further development for the 88000. This resource delves into the history, architecture, and eventual fate of the Motorola 88000, exploring why this promising technology became a "lost innovation" despite its advanced features and potential.

AIM Alliance: A strategic alliance formed in 1991 between Apple, IBM, and Motorola. The primary goal of the AIM alliance was to create a new, open standard RISC architecture to challenge Intel's dominance in the personal computer market. This collaboration led to the development of the PowerPC architecture.

History: Riding the Wave of RISC, and Missing the Crest

Background: Motorola's Dominance and the Emerging RISC Paradigm

The 1980s began on a high note for Motorola. Their Motorola 68000 microprocessor was a market leader, outperforming competitors with its advanced 32-bit architecture. This made it exceptionally well-suited for the rapidly growing workstation market. At a time when Intel's move into 32-bit computing was less aggressive, and other competitors like National Semiconductor faltered, Motorola held a dominant position in the non-Intel segment of the processor market. Intel commanded approximately 80% of the overall computer market, while Motorola controlled a significant 90% of the remainder.

However, the early 1980s witnessed the rise of a disruptive concept: RISC. Initially, there was considerable debate within the industry regarding the actual benefits of RISC. Skeptics argued that while RISC processors had simpler instructions, the resulting longer machine code programs could lead to performance bottlenecks due to increased memory access.

Machine Language: The lowest-level programming language, consisting of binary code directly executable by a computer's CPU. Each instruction in machine language corresponds to a basic operation that the processor can perform.

This debate was decisively settled by the mid-1980s with the emergence of the first RISC-based workstations. The performance gap was striking. For example, a Sun-3/80 workstation powered by a 20 MHz Motorola 68030 delivered around 3 MIPS (Millions of Instructions Per Second). In contrast, the first SPARC-based Sun-4/260, running at 16 MHz, achieved a significantly higher 10 MIPS. This dramatic performance difference convinced major vendors like Hewlett-Packard, DEC, and others to begin transitioning to RISC platforms.

MIPS (Millions of Instructions Per Second): A common measure of a computer's raw processing speed, indicating the number of instructions a processor can execute in one second. While MIPS can be a useful benchmark, it doesn't always accurately reflect real-world performance, especially across different architectures.

This shift towards RISC posed a significant threat to Motorola. The workstation market was one of Motorola's strongest and most profitable segments. Outside of workstations, Apple remained Motorola's only major customer. Other significant users of the 68000, like Atari and Commodore, were struggling in a market increasingly dominated by IBM PC compatibles. Motorola needed a RISC solution to stay competitive in the high-performance computing arena.

Motorola's Approach: Scoreboarding and Specialized Functionality

Motorola's approach to RISC was influenced by the understanding that RISC designs were fundamentally about optimizing the processor for the operations commonly used by compilers, particularly for Unix workstations and the C programming language. The pioneering IBM 801 project highlighted that compilers often used only a small subset of available instructions, primarily the simplest and fastest versions. The complex circuitry required for less frequently used, more complex instructions added overhead even to the simpler ones.

Compiler: A software program that translates source code written in a high-level programming language (like C, Java, Python) into machine code that can be executed by a computer's processor.

The RISC philosophy was to eliminate these underutilized, complex instructions, freeing up valuable chip space. This freed space was then used to increase the number of processor registers, which had a far greater impact on performance than the removed complex instructions. Essentially, RISC was a compiler-driven approach to processor design.

Processor Registers: Small, high-speed storage locations within the CPU used to hold data that the CPU is actively working on. Increasing the number of registers allows the CPU to keep more data readily available, reducing the need to access slower main memory and improving performance.

Motorola's technical documentation for the 88000 emphasized single-cycle instructions, large register files, and other hallmarks of RISC, notably avoiding the term "RISC" itself perhaps to differentiate their approach. Instead of directly competing with existing RISC designs, Motorola aimed to create "the world's most powerful processor." To achieve this ambitious goal, they drew inspiration from the CDC 6600 supercomputer, one of the fastest machines of its time.

CDC 6600: A pioneering supercomputer designed by Seymour Cray at Control Data Corporation (CDC) and introduced in 1964. It was renowned for its innovative architecture and high performance, setting a new standard for supercomputing at the time.

A key feature adopted from the CDC 6600 was scoreboarding. Scoreboarding is a technique that allows the CPU to examine instructions and execute them out of order if dependencies allow. The 88000's scoreboard could analyze instructions' register usage and immediately dispatch those that did not depend on the results of incomplete previous calculations. This instruction reordering enabled the processor to execute instructions whose data was readily available in registers or cache while waiting for data to be loaded from slower memory for other instructions. This technique could improve processor utilization by as much as 35%.

Scoreboarding: A hardware technique used in CPUs to allow for out-of-order instruction execution. The scoreboard tracks the availability of registers and functional units, enabling the CPU to execute instructions as soon as their operands are ready and the necessary resources are available, even if they are not in the original program order. This helps to improve instruction-level parallelism and overall performance.

The 88000 architecture also employed separate data and instruction address buses, a Harvard architecture characteristic. This design, while increasing pin count and complexity (128 pins just for the "P-bus" connecting caches and MMUs), was based on the observation that only about one-third of processor operations were memory-related; the rest involved operations on data already in registers or cache. A dedicated instruction pathway to an external instruction cache was therefore deemed highly beneficial.

Harvard Architecture: A computer architecture that uses physically separate storage and signal pathways for instructions and data. This contrasts with the Von Neumann architecture, where both instructions and data share the same memory space and pathways. Harvard architecture allows for simultaneous fetching of instructions and data, potentially improving performance, especially in applications with instruction-intensive workloads.

Initially, the caches and associated Memory Management Units (MMUs) were external chips. Cache controllers could be connected to either the data or instruction buses, and up to four controllers could be used on each bus, allowing for flexible cache configurations and scalability. Internally, the 88000 used three 32-bit buses, interconnected to internal units in ways optimized for reading and writing data to registers.

Memory Management Unit (MMU): A hardware component responsible for managing the computer's memory hierarchy. The MMU translates virtual addresses used by programs into physical addresses in RAM, and it also handles memory protection, cache management, and other memory-related functions.

Another innovative feature was built-in support for specialized co-processors, referred to as "Special Function Units" (SFUs). Beyond the standard instruction set, the 88000 reserved blocks of 256 instructions for use by co-processors. This was intended for designers who wanted to customize the system by adding specialized hardware units without altering the core ISA, ensuring software compatibility for standard functionality. Every 88000 processor included SFU1, which was the Floating-Point Unit (FPU).

Co-processor: A specialized processor designed to handle specific types of tasks more efficiently than the main CPU. Co-processors offload computationally intensive or specialized operations from the main processor, improving overall system performance. Examples include Floating-Point Units (FPUs) for numerical calculations, Graphics Processing Units (GPUs) for graphics rendering, and Digital Signal Processors (DSPs) for signal processing.

The 88000 also incorporated a delayed branch option in its branch and jump instructions. By appending ".n" to a branch instruction, the programmer could ensure that the instruction immediately following the branch (in the "delay slot") would execute before the branch target instruction, regardless of whether the branch condition was met. This was a technique used to improve instruction pipeline efficiency by filling the instruction slot that would otherwise be wasted during the branch operation. However, the use of the branch delay slot was later deprecated to maintain future compatibility and simplify programming.

Delayed Branch: A branch instruction design technique used in some pipelined architectures. In a delayed branch, the instruction immediately following the branch instruction (in the "delay slot") is always executed, regardless of whether the branch is taken or not. This allows the processor to keep the instruction pipeline full and avoid pipeline stalls that would occur if the branch target was fetched only after the branch condition was evaluated.

Release: High Performance, High Complexity, and High Price

By 1987, the industry widely anticipated Motorola's RISC processor, often referred to as "78000" (a nod to the earlier 68000). It was officially launched as the 88000 in April 1988.

The design complexity had a significant consequence: the CPU could not fit on a single chip. While the 68030, released a year prior, integrated 273,000 transistors, including the ALU and MMU, on a single chip (with an optional separate FPU chip), the 88000 architecture was split into two main chips. The MC88100, containing the ALU and FPU, had 750,000 transistors, and the MC88200, housing the MMU and a 16 KB static RAM cache, also had 750,000 transistors.

Arithmetic Logic Unit (ALU): The part of the CPU that performs arithmetic and logical operations.

Static RAM (SRAM): A type of semiconductor memory that is faster and more expensive than Dynamic RAM (DRAM). SRAM retains data as long as power is supplied, without needing periodic refreshing, making it suitable for cache memory.

Unlike the 68030 where the FPU was optional, a functional 88000 system required at least one MC88200. Systems could incorporate multiple MC88200 chips to create larger caches and provide multiple memory paths for enhanced performance.

Targeting the high end of the market, Motorola claimed the 88000 was the fastest 32-bit processor available at its release. Running at 20 MHz, it achieved 34,000 Dhrystones or 17 VUPS, compared to around 12 MIPS for a 12.5 MHz SPARC of similar vintage in a SPARCstation, or about 3.3 MIPS for a 20 MHz 68030. A 25 MHz version was also available, reaching 21 MIPS and 48,387 Dhrystones.

Dhrystone: A synthetic benchmark program used to measure the integer performance of processors. It is designed to be representative of typical programming tasks and provides a single number rating, often expressed in Dhrystones per second.

VUPS (VAX Unit of Performance): A benchmark used to measure computer performance relative to a VAX-11/780 minicomputer, which is defined as 1 VUP.

Motorola initially positioned the 88000 exclusively for high-end applications like "telecommunications, artificial intelligence, graphics, 3D animation, simulation, parallel processing, and supercomputers," suggesting the 68k series would continue to serve the workstation market. However, most potential customers largely ignored the 88000, leading to limited adoption beyond Motorola's own product lines.

Re-release: The Single-Chip MC88110 and the 88open Group

Recognizing the limited success of the initial release and the increasing adoption of other RISC architectures by their traditional customers, Motorola attempted to revive the 88000 with a single-chip version, the MC88110. In the late 1980s, companies like NeXT, Apple, and Apollo Computer were evaluating the 88000 for future use, but by the time the MC88110 became available in 1992, these companies had moved on to other designs.

To broaden adoption, Motorola initiated the 88open group, aiming to create an industry consortium and ecosystem similar to Sun Microsystems' efforts with SPARC. However, the 88open group failed to gain significant traction and did not achieve its goal of popularizing the 88000 architecture.

88open: An industry consortium formed by Motorola and other companies to promote the Motorola 88000 architecture. The group aimed to create an open standard for the m88k platform, fostering software and hardware development and encouraging wider adoption. Despite its efforts, 88open did not achieve widespread success.

Abandonment: The Rise of PowerPC and the End of the Line

In the early 1990s, Motorola shifted its focus dramatically by joining the AIM alliance. This collaboration aimed to develop a new RISC architecture based on IBM's POWER architecture. Motorola incorporated some features of the 88000, such as a compatible bus interface, into the new PowerPC architecture to provide a degree of upgrade path for their existing 88000 customer base. With the strategic shift to PowerPC, further development of the 88000 was promptly discontinued.

PowerPC: A RISC instruction set architecture developed jointly by Apple, IBM, and Motorola (the AIM alliance). PowerPC was designed to be a high-performance, scalable, and open architecture intended for a wide range of applications, from embedded systems to high-end servers and workstations. While initially successful and used by Apple in its Macintosh computers, PowerPC eventually lost market share to x86 architectures.

Architecture: A "Clean" and Advanced RISC Design

Similar to the Motorola 68000 before it, the 88000 was praised as a "clean" and well-designed architecture. It was a pure 32-bit load/store architecture, adhering strictly to the RISC principles of simplicity and efficiency. The 88000 featured a Harvard architecture with separate instruction and data caches, and separate data and address buses, enhancing memory bandwidth and reducing bottlenecks. It had a streamlined, powerful instruction set and utilized a flat address space, simplifying memory management for programmers.

Load/Store Architecture: A type of CPU architecture where the processor can only operate on data that is in registers. Memory access is restricted to dedicated load and store instructions, which move data between memory and registers. This design simplifies instruction set and allows for efficient pipelining.

A notable architectural feature was the unified register file used by both integer and floating-point instructions. This streamlined register management and potentially simplified instruction scheduling.

Implementations: From Two Chips to Single-Chip Integration

The initial implementation of the 88000 ISA was the MC88100 microprocessor. This chip integrated an FPU, reflecting the performance demands of its target market. It was designed to be paired with the MC88200 MMU and cache controller. This two-chip approach was intended to facilitate the construction of multiprocessor systems. A single MC88200 could support up to four MC88100 processors, enabling scalable performance.

However, this chip partitioning also increased the cost and complexity of building even basic single-processor systems. Requiring both the MC88100 and MC88200 chips, along with the necessary interconnections, made 88000-based systems more expensive and complex compared to competing architectures. This factor likely contributed to the 88000's limited market success.

The MC88100 also implemented a "Master/Checker" capability for fault tolerance. This feature, designed for critical applications, allowed for redundant operation using two or more MC88100 processors. In a Master/Checker configuration, one processor (the "master") operated normally, while a redundant "checker" processor executed the same instructions in parallel but with its outputs in a high-impedance state (effectively disconnected). The checker processor continuously compared its internal results with the outputs of the master processor, and if a mismatch occurred, it signaled an error. External logic would then handle the error condition.

Fault Tolerance: The ability of a system to continue operating correctly despite the failure of some of its components. Fault tolerance is crucial in critical applications where system downtime or data corruption can have severe consequences. Redundancy, error detection, and error correction are common techniques used to achieve fault tolerance.

The MC88110, the second-generation processor, addressed the packaging and cost issues of the original implementation. This chip integrated the CPU, FPU, MMU, and L1 cache into a single package, significantly simplifying system design and reducing cost. The MC88110 was also superscalar, capable of issuing and executing multiple instructions per clock cycle, further boosting performance.

Superscalar Architecture: A CPU architecture that can execute more than one instruction during a single clock cycle. Superscalar processors achieve instruction-level parallelism by having multiple execution units and fetching, decoding, and executing multiple instructions simultaneously.

An enhanced version, the MC88110MP, was developed at the request of MIT's *T project and included on-chip communication capabilities specifically for multiprocessor systems. A planned high-speed version, the MC88120, targeted speeds up to 100 MHz, but it was never released.

An embedded version, the MC88300, was under development in the early 1990s, intended for applications like automotive control systems (Ford Motor Company was a potential customer) and telecommunications. However, this project was eventually canceled, and Motorola offered a PowerPC design as a replacement, which Ford accepted. The cancellation of the MC88300 effectively marked the end of Motorola's commitment to the 88000 architecture across all market segments.

Products and Applications: Niche Successes and Limited Reach

Motorola produced its own line of single-board computers, the MVME series, designed for building ready-to-use 88000-based systems. They also offered the Series 900 "stackable" computers which used MVME boards. These systems were designed to be stacked vertically and interconnected with bus-like cables, an unconventional approach that did not gain popularity.

Third-party adoption of the 88000 was limited. The most significant user was Data General with their AViiON series of minicomputers and servers. The AViiON line achieved some level of popularity and remained in use for a period, but Data General later transitioned to Intel processors for subsequent models.

Encore Computer also built systems based on the m88k, including the Encore-91 and later the redesigned Infinity 90 series. However, the sales volume of these machines is unclear, and Encore eventually shifted to the Alpha architecture.

Tektronix introduced the XD88 line of graphics workstations in April 1989, utilizing the 88000 for graphics processing.

GEC Computers in the UK used the MC88100 in their GEC 4310, part of the GEC 4000 series. However, issues with memory management reportedly hampered its performance compared to earlier GEC 4000 models.

The BBN Butterfly model TC-2000, a parallel processing machine, was a notable application, scaling up to 512 MC88100 processors.

In the graphics and publishing sector, Linotype-Hell used the MC88110 in their "Power" workstations, running the DaVinci raster graphics editor for image manipulation.

The MC88110 was briefly considered for use in a never-released NeXT RISC Workstation. However, NeXT ultimately abandoned hardware development in 1993, and the project was canceled.

OMRON LUNA-88K workstations from Japan, featuring up to four 88000 processors, were used for a time on the Mach kernel project at Carnegie Mellon University, highlighting the 88000's capabilities in advanced operating systems research.

In the telecommunications industry, Northern Telecom (Nortel) adopted the MC88100 and MC88110 as the central processors in their DMS SuperNode family of telephone switches, a significant embedded application.

Smaller users included Alpha Microsystems, which initially planned to migrate to the 88k architecture but later opted for continued 68k development. NCD used the 88100 (without the 88200) in their 88K X-Terminals. Dolphin Server, a spin-off from Norsk Data, built servers based on the 88k, shipping around 100 systems between 1988 and 1992.

In a unique application, Virtuality employed the MC88110 as a graphics processor in their SU2000 virtual reality arcade machines, using one MC88110 per screen in each VR headset.

In the demanding embedded space, the "Tri-channel VMS Computer" in the F-15 S/MTD (Short Takeoff and Landing/Maneuvering Technology Demonstrator) aircraft used three 88000s in a triply redundant configuration for critical flight control functions.

Operating System Support: Unix and Open Source

Motorola provided its own Unix System V derivative, System V/88, for 88000-based systems. Two major releases were made: Release 3.2 Version 3 and Release 4.0 Version 3. Data General's AViiON systems ran DG/UX, their proprietary Unix variant.

The open-source community also provided support. OpenBSD ports exist for MVME systems, LUNA-88K workstations, and Data General AViiON systems. An unofficial experimental NetBSD port was also created for MVME systems, demonstrating continued interest in the architecture even after its commercial decline.

Conclusion: A Missed Opportunity in RISC History

The Motorola 88000, despite its advanced RISC architecture, innovative features like scoreboarding and SFUs, and impressive performance for its time, ultimately became a "lost innovation." Several factors contributed to its limited success:

• Late Market Entry: Arriving after SPARC and MIPS gave competitors a crucial head start in establishing market presence and developer ecosystems.
• Two-Chip Initial Implementation: The need for both the MC88100 and MC88200 for even basic systems increased cost and complexity, hindering adoption compared to single-chip RISC solutions.
• Delayed Single-Chip Solution: The MC88110, while technically advanced, arrived too late to recapture market interest, as potential customers had already committed to other architectures.
• Marketing and Positioning: Motorola's initial high-end focus and lack of clear messaging about the 88000's benefits in broader markets may have limited its appeal.
• Strategic Shift to PowerPC: Motorola's decision to join the AIM alliance and focus on PowerPC effectively ended further investment in and promotion of the 88000.

Despite its commercial fate, the Motorola 88000 remains a significant example of forward-thinking RISC design from the late 1980s and early 1990s. Its architectural innovations and performance capabilities demonstrate its potential to have been a major player in the RISC revolution. Its story serves as a valuable case study in the complex interplay of technology, market timing, strategic decisions, and industry dynamics that determine the success or failure of even the most promising technological innovations.